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S3C72C8/P72C8
PRODUCT OVERVIEW
1
OVERVIEW
PRODUCT OVERVIEW
The S3C72C8 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With an up-to-96-dot LCD direct drive capability flexible 16-bit timer/counter, and 4-chanel comparator, the S3C72C8 offers an excellent design solution for a low CDP and a card reader. Up to 28 pins of the 44-pin QFP or up to 26 pins of the 42-pin SDIP package can be dedicated to I/O. Eight vectored interrupts provide fast response to internal and external events. In addition, the S3C72C8's advanced CMOS technology provides for low power consumption.
OTP
The S3C72C8 microcontroller is also available in OTP (One Time Programmable) version, S3P72C8. S3P72C8 microcontroller has an on-chip 8K-byte one-time-programable EPROM instead of masked ROM. The S3P72C8 is comparable to S3C72C8, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C72C8/P72C8
FEATURES
Memory * * 512 x 4-bit RAM (including LCD display RAM) 8,192 x 8-bit ROM Interrupts * * * Four internal vectored interrupts Five external vectored interrupts Two quasi-interrupts
28 I/O Pins * * I/O: 26 pins (44-pin QFP, 42-pin SDIP) Output only: 2 pins (44-pin QFP)
Bit Sequential Carrier * Supports 16-bit serial data transfer in arbitrary format
LCD Controller/Driver * * * 12 segments and 8 common terminals (3, 4, and 8 common selectable) Internal resistor circuit for LCD bias All dot can be switched on/off Memory-Mapped I/O Structure * Data memory bank 15
Power-Down Modes * * * Idle mode (only CPU clock stops) Stop mode (main system oscillation stops) Sub system clock stop mode
8-bit Basic Timer * * 4 interval timer functions Watch-dog timer
Oscillation Sources * * * * * Crystal, ceramic, or RC for main system clock Crystal oscillator for subsystem clock Main system clock frequency: 0.4 MHz-6 MHz Subsystem clock frequency: 32.768 kHz CPU clock divider circuit (by 4, 8, or 64)
16-bit Timer/Counter 1 * * * * * * Programmable 16-bit timer/counter Arbitrary clock output External event counter External clock signal divider Configurable as two 8-bit timer/counters Serial I/O interface clock generator
Instruction Execution Times * * * 0.67, 1.33, 10.7 s at 6 MHz (main) 0.95, 1.91, 15.3 s at 4.19 MHz (main) 122 s at 32.768 kHz (subsystem)
Watch Timer * * * Time interval generation: 0.5 s, 3.9 ms at 32768 Hz Four frequency outputs to BUZ pin Clock source generation for LCD
Operating Temperature * - 40 C to 85 C
8-bit Serial I/O Interface * * * * 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable Internal or external clock source
Operating Voltage Range * 1.8 V to 5.5 V
Package Type * 44-pin QFP, 42-pin SDIP
Comparator * * 4 channel mode: internal reference (4-bit resolution) 3 channel mode: external reference
1-2
S3C72C8/P72C8
PRODUCT OVERVIEW
BLOCK DIAGRAM
8-Bit Timer/ Counter1A 8-Bit Timer/ Counter1B P2.0/CIN0/K0 P2.1/CIN1/K1 P2.2/CIN2/K2 P2.3/CIN3/K3
Watch Dog Timer 16-Bit Timer/ Counter XIN RESET XOUT Basic Timer
XTIN XTOUT Watch Timer
I/O Port 2 Interrupt Control Block I/O Port 3 Internal Interrupts I/O Port 5 Instruction Decoder SIO Program Status Word I/O Port 0 Stack Pointer I/O Port 1 Program Counter Clock Instruction Register LCD Driver/ Controller
COM0-COM3 COM4-COM7/ SEG15-SEG12 SEG0-SEG3/ P5.0-P5.3 SEG4-SEG7/ P6.0-P6.3 SEG8-SEG11/ P7.0-P7.3
P3.0/INTP30 P3.1/INTP31
P5.0-P5.3/ SEG0-SEG3
P6.0-P6.3/ SEG4-SEG7
I/O Port 6 Arithmetic and Logic Unit I/O Port 7
P7.0-P7.3/ SEG8-SEG11
S P0.0/ CK P0.1/SO P0.2/SI P0.3/BTCO P1.0/ CLO1/INT0 T P1.1/TCL1/INT1 P1.2/CLO/INT2 P1.3/BUZ/INT4
P4.0 P4.1
Output Port 4 44 QFP Only
512 x 4-Bit Data Memory
8 K Byte Program Memory
Comparator
Figure 1-1. S3C72C8 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C72C8/P72C8
PIN ASSIGNMENTS
44 43 42 41 40 39 38 37 36 35 34
P4.0 P4.1 P1.3/BUZ/INT4 P1.2/CLO/INT2 P1.1/TCL1/INT1 P1.0/TCLO1/INT0 COM0 COM1 COM2 COM3 COM4/SEG15
P2.0/CIN0/K0 P2.1/CIN1/K1 P2.2/CIN2/K2 P2.3/CIN3/K3 VDD VSS XOUT XIN TEST XTIN XTOUT
1 2 3 4 5 6 7 8 9 10 11
S3C72C8
(44-QFP-1010B)
33 32 31 30 29 28 27 26 25 24 23
COM5/SEG14 COM6/SEG13 COM7/SEG12 SEG11/P7.3 SEG10/P7.2 SEG9/P7.1 SEG8/P7.0 SEG7/P6.3 SEG6/P6.2 SEG5/P6.1 SEG4/P6.0
Figure 1-2. S3C72C8 44-QFP Pin Assignment Diagram
1-4
RESET P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P3.1/INTP31 P3.0/INTP30 SEG0/P5.0 SEG1/P5.1 SEG2/P5.2 SEG3/P5.3
12 13 14 15 16 17 18 19 20 21 22
S3C72C8/P72C8
PRODUCT OVERVIEW
COM1 COM0 P1.0/TCLO1/INT0 P1.1/TCL1/INT1 P1.2/CLO/INT2 P1.3/BUZ/INT4 P2.0/CIN0/K0 P2.1/CIN1/K1 P2.2/CIN2/K2 P2.3/CIN3/K3 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P0.3/BTCO P0.2/SI P0.1/SO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
COM2 COM3 COM4/SEG15 COM5/SEG14 COM6/SEG13 COM7/SEG12 SEG11/P7.3 SEG10/P7.2 SEG9/P7.1 SEG8/P7.0 SEG7/P6.3 SEG6/P6.2 SEG5/P6.1 SEG4/P6.0 SEG3/P5.3 SEG2/P5.2 SEG1/P5.1 SEG0/P5.0 P3.0/INTP30 P3.1/INTP31 P0.0/SCK
Figure 1-3. S3C72C8 42-SDIP Pin Assignment Diagram
(42-SDIP-600)
S3C72C8
1-5
PRODUCT OVERVIEW
S3C72C8/P72C8
Table 1-1. S3C72C8 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit and 4-bit read/write and test are possible. Individual pins are software configurable as input or output; Individual pins are software configurable as open-drain or push-pull output; Individual pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Same as port 0. Circuit Type E-1 Number 16 (22) 15 (21) 14 (20) 13 (19) Share Pin SCK SO SI BTCO
P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1
I/O
E-1
39 (3) 40 (4) 41 (5) 42 (6) 1 (7) 2 (8) 3 (9) 4 (10) 18 (24) 17 (23)
TCLO1/INT0 TCL1/INT1 CLO/INT2 BUZ/INT4 K0/CIN0 K1/CIN1 K2/CIN2 K3/CIN3 INTP30 INTP31
I/O
Same as port 0 except that port 2 is not configurable as n-channel open drain and is configurable as analog input pin. 2-bit I/O port 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output; Individual pins are software configurable as open-drain or push-pull output; 2-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 2-bit output port. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as open-drain or push-pull output. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output; Individual pins are software configurable as open-drain or push-pull output; 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Same as port5 Same as port5
F-8
I/O
E-3
P4.0 P4.1
O
E-2
44 43
P5.0-P5.3
I/O
H-13
19-22 (25-28)
SEG0-SEG3
P6.0-P6.3 P7.0-P7.3
I/O I/O
H-13 H-13
23-26 (29-32) 27-30 (33-36)
SEG4-SEG7 SEG8-SEG11
1-6
S3C72C8/P72C8
PRODUCT OVERVIEW
Table 1-1. S3C72C8 Pin Descriptions (Continued) Pin Name SEG0-SEG3 SEG4-SEG7 SEG8-SEG11 SEG12-SEG15 COM0-COM3 O O LCD segment display output pins LCD common signal output pins H-6 H-4 Pin Type I/O Description LCD segment display signal output pins Circuit Type H-13 Number 19-22 (25-28) 23-26 (29-32) 27-30 (33-36) 31-34 (37-40) 38-35 (2-1, 42-41) COM4-COM7 SCK SO SI BTCO TCLO1 TCL1 CLO BUZ RESET Xin, Xout XTin, XTout CIN0-CIN3 K0-K3 INT0 INT1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I - - I I/O I LCD common signal output pins Serial interface clock signal Serial data output Serial data input Basic timer overflow signal Timer/counter external clock output Timer/counter external clock input Clock output Frequency output to buzzer System RESET pin Clock input and output pins for main system clock Clock input and output pins for subsystem clock Analog input port for Comparator External interrupts. The triggering edge is selectable. External interrupts. The triggering edge for INT0 and INT1 is selectable. H-6 E-1 E-1 E-1 E-1 E-1 E-1 E-1 E-1 B - - F-8 F-8 E-1 34-31 (40-37) 16 (22) 15 (21) 14 (20) 13 (19) 39 (3) 40 (4) 41 (5) 42 (6) 12 (18) 8-7 (14-13) 10-11 (16-17) 1-4 (7-10) 1-4 (7-10) 39 (3) 40 (4) SEG12- SEG15 P0.0 P0.1 P0.2 P0.3 P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 - - - P2.0/K0 -P2.3/K3 P2.0/CIN0 -P2.3/CIN3 P1.0/TCLO1 -P1.1/TCL1 Share Pin P5.0-P5.3 P6.0-P6.3 P7.0-P7.3 COM7-COM4 -
1-7
PRODUCT OVERVIEW
S3C72C8/P72C8
Table 1-1. S3C72C8 Pin Descriptions (Continued) Pin Name INT2 INT4 INTP30 INTP31 TEST VDD VSS Pin Type I I I I - - Description Quasi-interrupt with detection of rising or falling edges. External interrupt with detection of rising or falling edges. Key scan interrupts inputs. System test pin Power supply pin Ground pin Circuit Type E-1 E-1 E-3 - - - Number 41 (5) 42 (6) 18-17 (24-23) 9 (15) 5 (11) 6 (12) Share Pin P1.2/CLO P1.3/BUZ P3.0, P3.1 - - -
NOTES: 1. Parentheses indicate pin number for 42-SDIP package. 2. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1-8
S3C72C8/P72C8
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD Pull-Up Resistor In
Schmitt Trigger Input
Figure 1-4. Pin Circuit Type B
VDD Pull-up Resistor Pull-Up Resistor Enable P-CH VDD
PNE
Data Output DIsable
I/O
Figure 1-5. Pin Circuit Type E-1
1-9
PRODUCT OVERVIEW
S3C72C8/P72C8
VDD PNE Data Out
Figure 1-6. Pin Circuit Type E-2
VDD Pull-Up Resistor Pull-Up Resistor Enable P-CH
PNE Ouput Disable Data Circuit Type E-4 LCON.1 I/O
Figure 1-7. Pin Circuit Type E-3
1-10
S3C72C8/P72C8
PRODUCT OVERVIEW
VDD PNE Data Out
Figure 1-8. Pin Circuit Type E-4
VDD
VLC1
COM Data Out LPOT.3 VLC4
VSS
Figure 1-9. Pin Circuit Type H-4
1-11
PRODUCT OVERVIEW
S3C72C8/P72C8
VDD
VLC1
VLC2
SEG/COM Data Out VLC3 LPOT.3
VLC4
VSS
Figure 1-10. Pin Circuit Type H-6
1-12
S3C72C8/P72C8
PRODUCT OVERVIEW
VDD
VLC2
SEG Data Output Disable Out VLC3
VSS
Figure 1-11. Pin Circuit Type H-7
1-13
PRODUCT OVERVIEW
S3C72C8/P72C8
VDD
Pull-Up Resistor Enable SEG Output DIsable
P-CH Circuit Type H-7
Data PNE
Circuit Type E-4
Figure 1-12. Pin Circuit Type H-13
1-14
S3C72C8/P72C8
PRODUCT OVERVIEW
VDD Pull-up Resistor Pull-Up Resistor Enable VDD P-CH
Data I/O Output DIsable
(Digital) INTK (Analog) External REF (P2.3 only) + Comparator REF Digital or Analog can be seleted by software.
Figure 1-13. Pin Circuit Type F-8
1-15
S3C72C8/P72C8
ELECTRICAL DATA
15
OVERVIEW
-- I/O capacitance
ELECTRICAL DATA
In this section, information on S3C72C8 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Main system clock oscillator characteristics -- Subsystem clock oscillator characteristics -- Comparator electrical characteristics -- A.C. electrical characteristics -- Operating voltage range Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request Miscellaneous Timing Waveforms -- A.C timing measurement points -- Clock timing measurement at Xin -- Clock timing measurement at XTin -- TCL1 timing -- Input timing for RESET signal -- Input timing for external interrupts and quasi-interrupts -- Serial data transfer timing
15-1
ELECTRICAL DATA
S3C72C8/P72C8
Table 15-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL Conditions - All I/O pins active - One I/O pin active All I/O pins active Output Current Low One I/O pin active Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 35 + 30 (Peak value) + 15 * Total for ports 0, 2-9 + 100 (Peak value) + 60 * Operating Temperature Storage Temperature TA Tstg - -
Duty . C C
Units V V V mA
mA
- 40 to + 85 - 65 to + 150
*
The values for Output Current Low ( IOL ) are calculated as Peak Value x
Table 15-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Symbol VIH1 VIH2 VIL1 VIL2 VOH Conditions Ports 0, 1, 2, 3, 5, 6, 7, RESET Xin, Xout, XTin, and XTout Ports 0, 1, 2, 3, 5, 6, 7, RESET Xin, Xout, XTin, and XTout VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 0, 1, 2, 3, 4, 5, 6, 7 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 0, 1, 2, 3, 4, 5, 6, 7 VDD = 1.8 V to 5.5 V IOL = 1.6 mA 0.4 VDD - 1.0 - Min 0.8 VDD VDD - 0.1 - - Typ - Max VDD VDD 0.2 VDD 0.1 - V V Units V
VOL
-
-
2.0
V
15-2
S3C72C8/P72C8
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Leakage Current Symbol ILIH1 Conditions VI = VDD All input pins except those specified below for ILIH2 VI = VDD Xin, Xout, XTin, and XTout All input pins except RESET, Xin, Xout, XTin, and XTout VI = 0 V Xin, Xout, XTin, and XTout VO = VDD All output pins VO = 0 V All output pins VI = 0 V; VDD = 5 V Ports 0-3, 5-7 expect RESET VDD = 3 V RL2 LCD Voltage Dividing Resistor |VLC1-COMi| Voltage Drop (i = 0-7 |VLC1-SEGx| Voltage Drop (x = 0-15) VLC1 Output Voltage VLC2 Output Voltage VLC3 Output Voltage VLC4 Output Voltage RLCD VDC VI = 0 V; VDD = 5 V, RESET VDD = 3 V Ta = 25 C - - - 20 3 A VI = 0 V - - Min - Typ - Max 3 Units A
ILIH2 Input Low Leakage Current ILIL1
20 -3 A
ILIL2 Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH ILOL RLI
-
-
-3
A
25
47
100
k
50 100 200 60
95 220 450 80
200 400 800 100 k
- 15 A per common pin
-
-
120
mV
VDS
- 15 A per segment pin
-
-
120
VLC1 VLC2 VLC3 VLC4
VDD = 1.8 V to 5.5 V, 1/5 bias LCD clock = 0 Hz, VLCD = VDD
0.8 VDD - 0.2 0.6 VDD - 0.2 0.4 VDD - 0.2 0.2 VDD - 0.2
0.8 VDD 0.6 VDD 0.4 VDD 0.2 VDD
0.8 VDD + 0.2 0.6 VDD + 0.2 0.4 VDD + 0.2 0.2 VDD + 0.2
V
15-3
ELECTRICAL DATA
S3C72C8/P72C8
Table 15-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (2) Conditions VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD2 (2) Idle mode VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD3 (3) IDD4 (3) IDD5 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz Min - Typ 3.0 2.3 1.5 1.0 1.3 1.2 Max 8.0 5.5 4.0 3.0 2.5 1.8 Units mA
6.0 MHz 4.19 MHz -
0.5 0.44 15.0 5.0 2.5
1.5 1.0 30 15 5 A
VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% VDD = 5 V 10% VDD = 3 V 10% SCMOD = 0100B SCMOD = 0000B XTin = 0V
0.5 0.2 0.1
3 3 2
NOTES: 1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, comparator, output port drive currents. 2. Data includes power consumption for subsystem clock oscillation. 3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 4. Every values in this table is measured when the power control register (PCON) is set to "0011B".
15-4
S3C72C8/P72C8
ELECTRICAL DATA
Table 15-3. Main System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
Xin Xout
Parameter Oscillation frequency (1)
Test Condition -
Min 0.4
Typ -
Max 6.0
Units MHz
C1
C2
Stabilization time (2)
Stabilization occurs when VDD is equal to the minimum oscillator voltage range; VDD = 3.0 V. -
-
-
4
ms
Crystal Oscillator
Xin
Xout
Oscillation frequency (1)
0.4
-
6.0
MHz
C1
C2
Stabilization time (2) External Clock Xin input frequency (1)
VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V -
- - 0.4
- - -
10 30 6.0
ms
Xin
Xout
MHz
Xin input high and low level width (tXH, tXL) RC Oscillator
Xin R Xout
- R = 25 k, VDD = 5 V
83.3 -
- 2
1250 -
ns MHz
Frequency
R = 40 k, VDD = 3 V
-
1
-
NOTES: 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
15-5
ELECTRICAL DATA
S3C72C8/P72C8
Table 15-4. Recommended Oscillator Constants (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Manufacturer Series Number (1) FCR FCR CCR M5 MC5 MC3 Frequency Range Load Cap (pF) C1 TDK 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 33
(2)
Oscillator Voltage Range (V) MIN 2.0 2.0 2.0 MAX 5.5 5.5 5.5
Remarks
C2 33
(2)
Leaded Type On-chip C Leaded Type On-chip C SMD Type
(3)
(3)
NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in.
Table 15-5. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration
XTin XTout
(1)
Parameter Oscillation frequency
Test Condition -
Min 32
Typ 32.768
Max 35
Units kHz
C1
C2
Stabilization time (2) External Clock XTin input frequency
(1)
VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V -
- - 32
1.0 - -
2 10 100
s
XTin
XTout
kHz
XTin input high and low level width (tXTL, tXTH)
-
5
-
15
s
NOTES: 1. Oscillation frequency and XTin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
15-6
S3C72C8/P72C8
ELECTRICAL DATA
Table 15-6. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
Table 15-7. Comparator Electrical Characteristics (TA = - 40 C + 85 C, VDD = 4.0 V to 5.5 V, VSS = 0 V) Parameter Input Voltage Range Reference Voltage Range Input Voltage Accuracy Internal External Symbol - VREF VCIN1 VCIN2 ICIN, IREF Condition - - - - - Min 0 0 - - -3 Typ - - - - - Max VDD VDD 150 150 3 Units V V mV mV A
Input Leakage Current
15-7
ELECTRICAL DATA
S3C72C8/P72C8
Table 15-8. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time (note) TCL1 Input Frequency TCL1 Input High, Low Width SCK Cycle Time Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V f TI1 VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V tTIH1, tTIL1 VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V tKCY VDD = 2.7 V to 5.5 V; Input Output VDD = 1.8 V to 5.5 V; Input Output SCK High, Low Width tKH, tKL VDD = 2.7 V to 5.5 V; Input Output VDD = 1.8 V to 5.5 V; Input Output SI Setup Time to SCK High tSIK VDD = 2.7 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output VDD = 1.8 V to 5.5 V; Input VDD = 1.8 V to 5.5 V; Output SI Hold Time to SCK High tKSI VDD = 2.7 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output VDD = 1.8 V to 5.5 V; Input VDD = 1.8 V to 5.5 V; Output 0.48 1.8 800 650 3200 3800 325 tKCY/2 - 50 1600 tKCY/2 - 150 100 150 150 500 400 400 600 500 - - ns - - ns - - ns - - ns - Min 0.67 1.33 0 - Typ - Max 64 64 1.5 1 - s MHz Units s
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
15-8
S3C72C8/P72C8
ELECTRICAL DATA
Table 15-8. A.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output Delay for SCK to SO Symbol tKSO Conditions VDD = 2.7 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output VDD = 1.8 V to 5.5 V; Input VDD = 1.8 V to 5.5 V; Output Interrupt Input High, Low Width RESET Input Low Width tINTH, tINTL tRSL INT0, INT1, INT2, INT4, K0- K3, INTP30, INTP31 Input 10 10 - - Min - Typ - Max 300 250 1000 1000 - - s s Units ns
NOTE: Minimum value for INT0 is based on a clock of 2tCY or 128 / fx as assigned by the IMOD0 register setting.
CPU CLOCK 1.5 MHz
Main Oscillator Frequency (Divided by 4) 6 MHz
1.05 MHz 0.75 MHz
4.2 MHz 3.0 MHz
15.6 kHz
1
2
1.8
3
4
5
6
7
SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, or 64)
Figure 15-1. Standard Operating Voltage Range
15-9
ELECTRICAL DATA
S3C72C8/P72C8
Table 15-9. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 1.8 V - Released by RESET Released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217 / fx
(2)
Max 5.5 10 - - -
Unit V A s ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
15-10
S3C72C8/P72C8
ELECTRICAL DATA
TIMING WAVEFORMS
Internal Reset Operation Stop Mode Data Retention Mode Idle Mode Operating Mode
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instruction RESET tWAIT tSREL
Figure 15-2. Stop Mode Release Timing When Initiated By RESET
Idle Mode
~ ~ ~ ~
Stop Mode Data Retention Mode
Normal Operating Mode
VDD
VDDDR Execution of STOP Instruction
tSREL
tWAIT Power-down Mode Terminating Signal (Interrupt Request)
Figure 15-3. Stop Mode Release Timing When Initiated By Interrupt Request
15-11
ELECTRICAL DATA
S3C72C8/P72C8
0.8 VDD Measurement Points 0.2 VDD
0.8 VDD
0.2 VDD
Figure 15-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx tXL tXH
XIN
VDD - 0.1 V 0.1 V
Figure 15-5. Clock Timing Measurement at XIN
1/fxt tXTL tXTH
XTIN
VDD - 0.1 V 0.1 V
Figure 15-6. Clock Timing Measurement at XTIN
15-12
S3C72C8/P72C8
ELECTRICAL DATA
1/fTI tTIL tTIH
TCL1
0.7 VDD 0.3 VDD
Figure 15-7. TCL1 Timing
tRSL
RESET 0.2 VDD
Figure 15-8. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1, 2, 4 K0 to K3 INTP30, INTP31
0.8 VDD 0.2 VDD
Figure 15-9. Input Timing for External Interrupts and Quasi-Interrupts
15-13
ELECTRICAL DATA
S3C72C8/P72C8
tKCY tKL SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKSO tKH
SO
Output Data
Figure 15-10. Serial Data Transfer Timing
15-14
S3C72C8/P72C8
MECHANICAL DATA
16
OVERVIEW
-- Pad diagram
#42
MECHANICAL DATA
This section contains the following information about the device package: -- Package dimensions in millimeters
#22
0-15
14.00 0.2
#1
#21
39.50 MAX 39.10 0.2
0.51 MIN
0.50 (1.77) 1.00
0.1 0.1
1.78
NOTE:
Dimensions are in millimeters.
Figure 16-1. 42-SDIP-600 Package Dimensions
3.30 0.3
5.08 MAX
3.50
0.2
0.2
5
+0 - 0 .1 .05
42-SDIP-600
15.24
16-1
MECHANICAL DATA
S3C72C8/P72C8
13.20 0.3 0-8 10.00 0.2 0.15
+ 0.10 - 0.05
13.20 0.3
10.00 0.2
44-QFP-1010B
0.80 0.20 #1 0.80
+ 0.10
0.10 MAX
#44
0.35 - 0.05 (1.00)
0.05 MIN 2.05 0.10 2.30 MAX
NOTE: Dimensions are in millimeters.
Figure 16-1. 44-QFP-1010B Package Dimensions
16-2
S3C72C8/P72C8
S3P72C8 OTP
17
OVERVIEW
S3P72C8 OTP
The S3P72C8 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72C8 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P72C8 is fully compatible with the S3C72C8, both in function and in pin configuration. Because of its simple programming requirements, the S3P72C8 is ideal for use as an evaluation chip for the S3C72C8.
44 43 42 41 40 39 38 37 36 35 34
P4.0 P4.1 P1.3/BUZ/INT4 P1.2/CLO/INT2 P1.1/TCL1/INT1 P1.0/TCLO1/INT0 COM0 COM1 COM2 COM3 SEG15/COM4
P2.0/CIN0/K0 P2.1/CIN1/K1 SDAT/P2.2/CIN2/K2 SCLK/P2.3/CIN3/K3 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT
1 2 3 4 5 6 7 8 9 10 11
S3P72C8
33 32 31 30 29 28 27 26 25 24 23
COM5/SEG14 COM6/SEG13 COM7/SEG12 SEG11/P7.3 SEG10/P7.2 SEG9/P7.1 SEG8/P7.0 SEG7/P6.3 SEG6/P6.2 SEG5/P6.1 SEG4/P6.0
Figure 17-1. S3P72C8 44-QFP Pin Assignments
RESET/RESET RESET BTCO/P0.3 SI/P0.2 SO/P0.1 SCK/P0.0 INTP31/P3.1 INTP30/P3.0 P5.0/SEG0 P5.1/SEG1 P5.2/SEG2 P5.3/SEG3
12 13 14 15 16 17 18 19 20 21 22
17-1
S3P72C8 OTP
S3C72C8/P72C8
COM1 COM2 P1.0/TCLO1/INT0 P1.1/TCL1/INT1 P1.2/CLO/INT2 P1.3/BUZ/INT4 P2.0/CIN0/K0 P2.1/CIN1/K1 SDAT/P2.2/CIN2/K2 SCLK/P2.3/CIN3/K3 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET P0.3/BTCO P0.2/SI P0.1/SO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
COM2 COM3 COM4/SEG15 COM5/SEG14 COM6/SEG13 COM7/SEG12 SEG11/P7.3 SEG10/P7.2 SEG9/P7.1 SEG8/P7.0 SEG7/P6.3 SEG6/P6.2 SEG5/P6.1 SEG4/P6.0 SEG3/P5.3 SEG2/P5.2 SEG1/P5.1 SEG0/P5.1 P3.0/INTP30 P3.1/INTP31 P0.0/SCK
Figure 17-2. S3P72C8 42-SDIP Pin Assignments
S3P72C8
17-2
S3C72C8/P72C8
S3P72C8 OTP
Table 17-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P2.2 Pin Name SDAT Pin No. 3 (9) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to + 5 V during programming.
P2.3 TEST
SCLK VPP(TEST)
4 (10) 9 (15)
I/O I
RESET VDD/VSS
RESET VDD/VSS
12 (18) 5/6 (11/12)
I I
NOTE: Parentheses indicate pin number for 42-SDIP package.
Table 17-2. Comparison of S3P72C8 and S3C72C8 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 8 Kbyte EPROM 1.8 V to 5.5 V VDD = 5 V, VPP(TEST)=12.5V 44-QFP, 42-SDIP User Program 1 time 44-QFP, 42-SDIP Programmed at the factory S3P72C8 S3C72C8 8 Kbyte mask ROM 1.8 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P72C8, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 17-3 below. Table 17-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode
NOTE: "0" means Low level; "1" means High level.
17-3
S3P72C8 OTP
S3C72C8/P72C8
Table 17-4. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (2) Conditions VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD2 (2) Idle mode VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD3 (3) IDD4 (3) IDD5 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz Min - Typ 3.0 2.3 1.5 1.0 1.3 1.2 Max 8.0 5.5 4.0 3.0 2.5 1.8 Units mA
6.0 MHz 4.19 MHz -
0.5 0.44 15.0 5.0 2.5
1.5 1.0 30 15 5 A
VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% VDD = 5 V 10% VDD = 3 V 10% SCMOD = 0100B SCMOD = 0000B XTIN = 0V
0.5 0.2 0.1
3 3 2
NOTES: 1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, comparator, output port drive currents. 2. Data includes power consumption for subsystem clock oscillation. 3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 4. Every values in this table is measured when the power control register (PCON) is set to "0011B".
17-4
S3C72C8/P72C8
S3P72C8 OTP
CPU CLOCK 1.5 MHz
Main Oscillator Frequency (Divided by 4) 6 MHz
1.05 MHz 0.75 MHz
4.2 MHz 3.0 MHz
15.6 kHz
1
2
1.8
3
4
5
6
7
SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, or 64)
Figure 17-3 Standard Operating Voltage Range
17-5
S3P72C8 OTP
S3C72C8/P72C8
NOTES
17-6

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